CISC processors suit virtually every task, but RISC processors can do more with less power. The RISC vs. CISC battle has moved into the data center, with compelling pros for RISC.
>RISC vs. CISC processors
Today’s x86 processor designs are an amalgamation of features and functionality from the last 30 years, right up to today’s Intel-VT and AMD-V instructions to support hardware-assisted virtualization.
But there’s a problem with this complex instruction set computing (CISC) approach; every new instruction or feature adds tens of thousands of transistors to the processor die, adding power demands and latency even if the instructions are rarely used. The chip is extremely versatile, but it runs hot and sucks power with ever-increasing clock speeds.
Processors run much more efficiently when tailored to a specific task. Reduced instruction set computing (RISC) strips out unneeded features and functionality, and builds on task-specific capabilities. Simpler, more reliable RISC processors provide the same effective computing throughput at a fraction of the power and cooling.
The question in CISC vs. RISC arguments is versatility vs. efficiency. Traditional x86 CISC processors can tackle almost any computing task using an extraordinarily comprehensive instruction set. This made CISC the preferred chip design for general-purpose computing platforms: enterprise servers, desktop PCs and laptop/notebook systems.
Purpose-built RISC processors sacrifice versatility for efficiency. Removing unneeded instructions dramatically reduces the processor’s transistor count. Tackling fewer tasks in hardware means those tasks are performed faster, even at lower clock speeds (less power) than a full x86 CISC counterpart.
Printers, home routers, and even multifunction telephones and remote controls use RISC processors, and the concept is growing dramatically for fully featured computing platforms. A tablet or smartphone’s RISC processor can deliver smooth video playback, fast webpage display and a responsive user interface for many hours on a battery charge, with no cooling devices. This same chip design paradigm is systematically finding traction in data center systems.<